Semiconductor large scale integrated circuits (simply, LSI in the following) are shipped after the phases of design, manufacturing and test. Here, test means the operation of determining whether products are defective or defect free by applying test vectors (simply, vectors in the following) to LSI (concretely, combinational portion in a sequential circuit) manufactured based on design data and by comparing the response with expected value. The rate of defect free LSI products which pass the test (yield) is said to be the key of semiconductor industry because the quality, reliability and cost of LSI depends on it greatly. And at-speed testing conducts tests of LSI at the operating speed of actual use. When vectors are composed of initialization pattern and of launch pattern which detect faults, as shown in FIG. 5, at-speed testing is conducted as follows. The initialization pattern is applied to combinational circuit at the rising timing of shift pulse SL. Subsequently, the launch pattern is applied to the combinational circuit at the rising timing of pulse C1. And the resulted response of the combinational circuit is observed at the rising timing of pulse C2. The testing state of the combinational circuit is finished at the rising timing of shift pulse S1.
High launch-induced switching activity in a combinational circuit caused by applying the launch pattern after pulse C1 results in frequent decrease of power supply voltage (IR-drop) and increase of power supply noise, increasing the delay in the combinational circuit. If the delay increases too much, the adequate response which should be obtained at the timing of pulse C2 cannot be obtained, resulting in capturing wrong response to flip-flops in the sequential circuit by timing error. Consequently, test malfunction occurs where a product is wrongly determined as defective because the response from the combinational circuit doesn't match the expected value. And test malfunctions occur frequently in at-speed testing where the timing gap between capture C1 and capture C2 is narrow.
There is a method for generating a vector which doesn't cause IR-drop, called X-filling technique. When detecting one or a plurality of kinds of faults to be detected in an LSI (concretely, combinational portion in a sequential circuit), it is possible to detect the faults by assigning logic values 0 or 1 only to a part of bits which relates to detecting the faults in the vector. The rest of the bits which don't relate to detecting the faults (that is, which don't decrease fault coverage) in the vector are don't-care-bits (X-bits). X-filling technique is a technique to assign logic values 0 or 1 to the don't-care-bits for a particular purpose. For example, when the response Fp(V) and Fs(V) are obtained for a vector V which is composed of Vp and Vs, as shown in FIG. 6, the difference can be decreased between Vs and Fs(V). Here, in the FIG. 6, pi (i=1 to 6) and qi (i=1 to 6) denotes input lines and output lines of the combinational circuit, respectively 10. In Non-Patent Document 1, don't-care-bit identification for every test input by use of a method for checking in order whether each of the bits can be a don't-care-bit is described.    Non-Patent Document 1: R. Sankaralingam, R. Oruganti, and N. Touba, “Reducing Power Dissipation during Test Using Scan Chain Disable”, Proc. VLSI Test Symp., pp. 319-324, 2001.